The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 1999

Filed:

Jul. 30, 1997
Applicant:
Inventors:

Sudhir Sharma, Plano, TX (US);

Michael E Runas, McKinney, TX (US);

Robert M Nally, Plano, TX (US);

Assignee:

Cirrus Logic, Inc., Fremont, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518905 ; 36523006 ;
Abstract

A memory system 104 includes an array 200 of memory calls arranged in rows and columns and circuitry 208 for selectively performing logic operations on a bit of data stored in a selected call using a bit of received modifying data and a mode data bit for selecting a logic operation for performance. Circuitry 208 for modifying during an OR logic operation writing bit of the modifying data into the cell when the bit of modifying data is a logic one and maintaining an existing bit stored in call when the bit of modifying data is a logic zero. Memory system 104 further includes circuitry 207, 210 for receiving and latching the mode data and the modifying data through a single port.


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