The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 1999

Filed:

Aug. 15, 1997
Applicant:
Inventors:

Vladimir Koifman, Rishon Le Zion, IL;

Yachin Afek, Kfar Saba, IL;

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F / ;
U.S. Cl.
CPC ...
323315 ; 323907 ; 323314 ;
Abstract

A reference circuit (200') has bipolar transistors (216, 226) providing a voltage difference .DELTA.V of base-emitter voltages .vertline.V.sub.BE .vertline. and has resistors (210/R.sub.1, 220/R.sub.2) for adding a current I.sub.R1 resulting from .DELTA.V and a current I.sub.R2 resulting from of base-emitter voltage .vertline.V.sub.BE .vertline. of one bipolar transistor (216 or 226) so that a resulting temperature coefficient TC.sub.TOTAL of said currents I.sub.R1 and I.sub.R2 is compensated. The circuit (200') has voltage transfer units (260, 270) which transfer .DELTA.V to the resistors (210/R.sub.1, 220/R.sub.2) so that the resistors (210/R.sub.1, 220/R.sub.2) do not substantially load the bipolar transistors (216, 226). The voltage transfer units (260, 270) have input stages with n-channel FETs. A control unit (241) which is coupled to the bipolar transistors (216, 226) adjusts input voltages (.vertline.V.sub.CE .vertline.) at the voltage transfer units (260, 270) to temperature changes, so that the n-channel FETs operate in an active region. The control unit (241) has a voltage source (290) providing a voltage V.sub.DS REF which is similary temperature and process depending as a drain-source voltage of the n-FETs.


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