Method for avoiding contention during boundary scan testing

Abstract

According to the present invention, methods for testing interconnections on an electronic assembly in accordance with the disclosed embodiments eliminate some or all signal line contention during boundary scan testing. Each of these methods assumes that a first sequence of test patterns for testing the interconnects has been generated. A method in accordance with the first embodiment determines a safe pattern, and inserts the safe pattern between every two patterns in the first sequence of test patterns to generate a second sequence of test patterns. A method in accordance with the second embodiment analyzes the first sequence of test patterns, determines when a transition between two test patterns may cause possible signal contention, and inserts a safe test pattern between the two to generate a second sequence of test patterns. When a transition between two test patterns may potentially cause contention, the transition is said to be unsafe. The safe test pattern in the second embodiment may be a single safe test pattern for all transitions, or may be a safe test pattern that is derived from the two test patterns that generate the unsafe transition. A method in accordance with the third embodiment analyzes the first sequence of test patterns, reorders the test patterns to minimize the number of unsafe transitions, and then inserts a safe test pattern between patterns at unsafe transitions, if any, to assure that no signal contention occurs during boundary scan testing. The safe test pattern for the third embodiment may be a single test pattern, or may be a test pattern that is derived from the test patterns that generate the unsafe transition.