The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 01, 1999
Filed:
Jan. 31, 1997
Jorge E Lach, Lexington, MA (US);
George R Plouffe, Jr, Bradford, MA (US);
Gerald L Marchessault, Lawrence, MA (US);
Sun Microsystems, Inc, Palo Alto, CA (US);
Abstract
A diagnostic subsystem is used in a digital device in a digital computer system includes a diagnostic register, a device output control circuit and a diagnostic register reset circuit. The diagnostic register includes a plurality of stages each of which is associated with one of the types of transfers over the bus. Each stage is selectively conditionable by the digital computer system's processor. The device output control circuit controls transfers by the digital device over the bus. The device output control circuit enables the digital device, when it is to engage in a transfer, to transfer information correctly when the associated stage is set and to transfer information incorrectly when the stage has the set condition. For transfers in which the one device is to transmit information over the bus, the incorrectly transmitted information causes error checking circuitry in other devices in the system to generate error indications, which are provided to the processor. On the other hand, for transfers in which the device is to receive information over the bus, correctly received information causes error checking circuitry in the device to generate an error indication, which is also provided to the processor. The diagnostic register reset circuit enables said the respective stages to be conditioned to said reset condition following a transfer of incorrect information during a transfer of said associated transfer type, so that the one device engages in such a transfer once after being enabled by the processor.