Data processing device with time-multiplexed memory bus

Abstract

A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The central processing unit further contains two auxiliary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle. A second memory bus is also connected to the on-chip RAM and ROM, and to the peripheral ports, so that access to one of the memory elements via said first memory bus can occur simultaneously with, and independently from, access to another of said memory elements via said second memory bus. The on-chip memory and external memory are all mapped into a single memory address space, which allows simultaneous program and data fetches via the two memory buses, or a program and data fetch during the same cycle using the first time-multiplexed bus.