Method and apparatus for the sharing of a memory device by multiple

Abstract

A method and apparatus for controlling the access of multiple processors to a shared memory device in a computer or other processor-based system. An exemplary embodiment includes an embedded processor and a host processor, both of which share access to a single-port random access memory (RAM). An access control circuit is provided which includes a control register with a first storage element corresponding to the embedded processor and a second storage element corresponding to the host processor. The access control circuit utilizes access request bits stored in the first and second storage elements to generate a select signal which is applied to the select signal inputs of a group of multiplexers. The multiplexers select either the embedded processor or host processor control, address and data signal lines for connection to the single-port RAM. The access control circuit is configured such that the first processor to successfully set the access request bit in its corresponding storage element is granted temporary exclusive access to the RAM. The storage elements are interconnected such that the output of a given element drives a reset input of the other element. Once a given processor sets its access request bit and is thereby granted access to the shared RAM, the storage element interconnection prevents the other processor from setting its access request bit until the given processor relinquishes control of the RAM.