Circuit and method for controlling a redundant memory cell in an

Abstract

A circuit and method are shown for controlling a redundant memory cell of an integrated memory circuit. The circuit includes a decoder, a precharge enable unit, a redundant controller, a redundant enable signal generator, and a redundant memory cell array. The precharge enable unit is connected to the decoder, and responds to a precharge enable signal by precharging the output terminal of decoder. The decoder responds to a first row address signal by discharging the output terminal of the decoder unless the value of the row address signal corresponds to a programmed address of the decoder. The redundant enable signal generator samples the voltage level of the output terminal of the decoder under control of a redundant control signal of the redundant controller in order to generate a redundant cell enable signal. The redundant controller generates the redundant control signal in response to a second row address signal, where the redundant controller delays the redundant control signal by a predetermined time interval in response to a stress test signal which is active during a stress test in order to allow the decoder sufficient time to discharge the output terminal during the stress test. The redundant memory cell array is connected to the redundant enable signal generator and responds to the redundant enable signal.