Verification system for circuit simulator

Abstract

An electronic circuit verification system and method includes an HDL circuit simulator and a circuit simulation verifier that pass control back and forth between each other, and that cooperate so as to perform circuit verification tasks than would be very difficult to perform using only the HDL circuit simulator. The circuit simulation verifier is coupled to the HDL circuit simulator so as to control the HDL circuit simulator's operation, including specifying conditions under which the HDL circuit simulator is to stop simulation of a specified circuit and specifying input signal waveforms to be used by the HDL circuit simulator. The circuit simulation verifier receives signal waveforms generated by the HDL circuit simulator for specified watched signals. The circuit simulation verifier then determines whether predefined logical combinations of the watched signals meet specified operational correctness and/or performance criteria within specified time frames. A test bench is composed of a sequence of instructions, including instructions indicating when to activate various operational correctness and/or performance criteria, instructions for sending commands to the HDL simulator, and branch or condition instructions for controlling which instructions of the test bench are to be executed. Furthermore, a test bench can include instructions for generating a plurality of distinct threads of execution, each of which is composed of its own sequence of instructions, and furthermore can include instructions for conditionally spawning additional threads of execution when specified combinations of Expect Events are satisfied in specified ones of the threads.