The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 1999

Filed:

Apr. 08, 1997
Applicant:
Inventor:

Clifton J Williamson, Soquel, CA (US);

Assignee:

Seagate Technology, Inc., Scotts Valley, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 3711 ;
Abstract

The present invention pertains to an apparatus and method for determining at most four error locations of RS encoded data read from a storage medium. The error location polynomial solver includes a controller, a multiplexer, storage registers, a data flow control unit, and various GF(256) arithmetic units. The GF(256) arithmetic units include GF(256) multiply unit, a GF(256) logarithmic ROM, a GF(256) anti-logarithmic ROM, a GF(256) square root unit, a GF(256) quadratic root finder, and a specialized integer division unit. The controller directs the operation of each of these components to perform one or more equation solver procedures that determine the appropriate number of roots. In an embodiment of the present invention, the controller is implemented as a state machine. The controller receives four coefficients representing an error location polynomial. The degree of the error location polynomial is determined in order for the controller to execute an appropriate equation solver procedure. The controller can execute one of four equation solver procedures based on the degree of the received error location polynomial.


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