The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 18, 1999
Filed:
Jan. 27, 1997
Tokuya Osawa, Tokyo, JP;
Hideshi Maeno, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
In a normal mode, a logic test signal (LOGTEST), a RAM test signal (RAMTEST), and a shift mode signal (SM) are set to '0'. A RAM core (91) is synchronously written and asynchronously read. In a logic test mode, the RAM test signal (RAMTEST) is set to '0', and the logic test signal (LOGTEST) is set to '1'. In a RAM test mode, the RAM test signal (RAMTEST) is set to '1', and the logic test signal (LOGTEST) is set to '0'. A scan path (3a) is used both as a scan path provided between logic portions (82, 83) in the logic test and as a scan path provided at the output of the RAM core (91) in the RAM test. The scan path provides a high area utilization efficiency.