The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 18, 1999
Filed:
Sep. 03, 1997
Vassili Kitch, San Ramon, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A process for forming a via in a semiconductor device using a self-aligned metal pillar to connect metal layers separated by a dielectric. A first aluminum layer is formed on an oxide layer overlying a semiconductor substrate, a titanium nitride layer is formed on the aluminum layer and finally a second aluminum layer is formed on the titanium nitride layer. In one continuous etching step, the stack of aluminum/titanium nitride/aluminum is then patterned and etched. A first dielectric is deposited overlying the exposed regions of the oxide layer and the formed metal stack. The wafer is then planarized exposing the top of the second aluminum layer. The wafer is again patterned and the second layer of aluminum is etched using the titanium nitride as an etch stop. A second dielectric is deposited to fill the resulting gaps and CMP processes are used to planarize the wafer and expose the top of the aluminum pillar. A third aluminum layer is formed on the overlying dielectric to make electrical contact to the exposed surface of the pillar.