The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 1999

Filed:

Feb. 13, 1997
Applicant:
Inventor:

Mieko Suzuki, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438633 ; 438692 ; 438699 ;
Abstract

A semiconductor device is formed with an interlayer insulation layer having its high flatness. A metal wiring is formed on a silicon substrate via a silicon oxide layer. A multi-layer silicon oxide layer that is to be the interlayer insulation film is formed over the insulation layer and the metal wiring. The multi-layer silicon layer consists of an upper most first silicon oxide layer, a lower most third silicon oxide layer and an intermediate second silicon oxide layer. The second silicon oxide layer has higher polishing rate than the first and third silicon oxide layer. By performing chemical mechanical polishing for the multilayer silicon oxide layer, a step formed by the presence of the metal layer can be satisfactorily eliminated fox planarizing the surface of the interlayer insulation film.


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