The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 1999

Filed:

Nov. 20, 1995
Applicant:
Inventors:

Thang M Tran, Austin, TX (US);

Marty L Pflum, Austin, TX (US);

David B Witt, Austin, TX (US);

William M Johnson, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
711132 ; 711118 ; 711120 ; 395376 ;
Abstract

A microprocessor including a pair of caches is provided. One of the pair of caches is accessed by stack-relative memory accesses from the decode stage of the instruction processing pipeline. The second of the pair of caches is accessed by memory accesses from the execute stage of the instruction processing pipeline. When a miss is detected in the first of the pair of caches, the stack-relative memory access which misses is conveyed to the execute stage of the instruction processing pipeline. When the stack-relative memory access accesses the second of the pair of caches, the cache line containing the access is transmitted to the first of the pair of caches for storage. The first of the pair of caches selects a victim line for replacement when the data is transferred from the second of the pair of caches. If the victim line has been modified while stored in the first cache, then the victim line is stored in a copyback buffer. A signal is asserted by the first cache to inform the second cache of the need to perform a victim line copyback. Requests from the execute stage of the instruction processing pipeline are stalled to allow the copyback to occur.


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