Microprocessor clocking control system

Abstract

A computer system is provided with microprocessor clocking control by providing a clock having output timing signals which vary based on input signals to the clock, setting timing parameters for the clock using a service processor which sends the input signals to the clock, and controlling the primary processor using the output timing signals from the clock. The service processor can be used to modify a pulse width of at least one of the output timing signals, and to delaying a first one of the output timing signals with respect to a second one of the output timing signals. Separate clock signals can be provided for the primary processor and other system components, such as a cache connected to the primary processor, a memory device of the computer system, or an input/output device of the computer system. The clock has a programmable duty-cycle control circuit. The duty-cycle control circuit may use delay chains having a plurality of individually selectable delay elements.