Semiconductor memory device having fast data writing mode and method of

Abstract

Disclosed is a semiconductor memory device including a normal memory array and preliminary memory array enabling a mutual data transfer. Word lines in the normal memory array and those in the preliminary memory array are controlled by separate row decoders and separate word drivers. Bit lines and sense amplifiers are provided commonly to the normal memory array and the preliminary memory array. When test data is written in a predetermined pattern into the normal memory array, data corresponding to the predetermined pattern is written in advance for each memory cell in the preliminary memory array. Then, after the row decoder and word driver for the preliminary memory array are enabled so that the word lines in the preliminary memory array are activated, the row decoder and word driver for the normal memory array are enabled so that the word lines in the preliminary memory array are activated. Thus, data signals read from memory cells of one row in the normal memory array are simultaneously amplified by the sense amplifiers via the bit lines and then transferred via the bit lines to memory cells of one row in the preliminary memory array. In this result, the test data are written at one time into the memory cells of one row in the normal memory array.