The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 11, 1999
Filed:
Jul. 18, 1996
Vilas V Gupte, Fremont, CA (US);
Sanjay Adkar, Saratoga, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
Systems and methods of verifying the design of the ASIC during design and implementation phases are provided. The ASIC design is verified utilizing information from a system simulation in the customer's system environment. During system simulation, the invention captures 'golden' vectors that may be used to test the ASIC during stand-alone simulation. The outputs generated by the ASIC during stand-alone simulation are compared to the outputs generated during the system simulation. Thus, the customer's system simulation is reproduced without having to reproduce the customer's system environment which allows the operation of the ASIC to be verified during various states of synthesis. Additionally, the test bench for testing the ASIC in stand-alone simulation is automatically generated eliminating the need for the user to manually generate a test bench.