Method and apparatus for reducing skew among input signals within an

Abstract

The integrated circuit includes an input path circuit with an address path having an input buffer for providing address signals to a register. A separate clock path having an input buffer provides a clock signal for clocking the register. The input path circuit also includes one or more decode units each having a number of logic gate cells such as NAND gate cells or NOR gate cells. Circuitry is provided within the logic gates for reducing timing delay differences between propagation of multiple bit binary signals, such as address signals, through the logic gates. In an exemplary NAND gate described herein, reduction in timing delay differences is achieved by positioning an additional PMOS device along a current path between a power source and an output path otherwise including only a pair of parallel PMOS devices. The additional PMOS device acts as a choke on the current flow through the pair of parallel PMOS devices thereby reducing propagation delay differences which would otherwise occur as a result of either only one or both of the parallel PMOS devices operating to pull up the output path. Similar circuit modifications are provided within NOR gates or logic gates.