Semiconductor device having misfet sram cells in which active regions

Abstract

A semiconductor device is constituted by an arrangement of MISFET type SRAM cells structured such that near the edge of active regions of the driver MISFETs in each memory cell, at least one of the source and drain regions of each driver MISFET is offset against the gate electrode of that MISFET. This offset structure is formed by implantation of impurities using a mask covering the edge proximity of the active regions. Moreover, near one edge of the gate electrode of each driver MISFET in an SRAM memory cell, the gate length of that driver MISFET is at least twice the gate length of the MISFET which has the shortest gate length and which constitutes part of a memory cell or a peripheral circuit. Also, at one edge of the gate electrode of each driver MISFET in an SRAM memory cell, the spacing distance between the gate electrode of that driver MISFET and the gate electrode (word line) of a transfer MISFET is made substantially the same in at least two directions. Also, the spacing distance between the gate electrode of each driver MISFET and the gate electrode of a corresponding driver MISFET in an adjacent memory cell is made substantially the same as the spacing distance between the gate electrode of each driver MISFET and the gate electrode (word line) of the transfer MISFET connected thereto.