Digital delay locked loop circuit using synchronous delay line

Abstract

A digital locked loop circuit having a synchronous delay line, an input node for receiving an external clock signal, and an internal clock node for generating an internal clock signal synchronized with the external clock signal. The digital locked loop circuit includes; a delay buffer for generating a first clock signal by delaying the external clock signal by a predetermined time; a main delay for generating a second clock signal by delaying the first clock signal by a predetermined time; a first delay line consisting of a plurality of serially connected first unit delays, each of the plurality of first unit delays generating a first unit delay output signal by delaying the second clock signal by a predetermined unit length; a second delay line consisting of a plurality of serially connected second unit delays, each of the plurality of second unit delays generating a second unit delay output signal by delaying the first clock signal by a predetermined unit length; switching means for coupling the first clock signal to the internal clock node in response to an enable signal, the switching means having a plurality of switches, each of the plurality of switches connected between an output node of a corresponding second unit delay of the second delay line and the internal clock node; and phase comparing means for generating the enable signal for a predetermined switch of the plurality of switches when the first clock signal is in phase with at least one first unit delay output signal, the phase comparing means being connected between an output node of a first unit delay and an enable port of a corresponding switch of the plurality of switches of the switching means.