The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 04, 1999

Filed:

Jun. 18, 1997
Applicant:
Inventors:

Nadav Ben-Efraim, Cupertino, CA (US);

Christopher Keate, Santa Clara, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L / ; H04H / ;
U.S. Cl.
CPC ...
375344 ; 375345 ; 375371 ; 375374 ; 455-32 ; 348731 ; 348733 ;
Abstract

An improved DBS receiver front end architecture having a voltage controlled oscillator for frequency synthesis. The voltage controlled oscillator includes a tank circuit having an adjustable resonance frequency which may be varied over an octave. A tuning oscillator drives the tank circuit and provides a signal having that resonance frequency to a range extender which provides a tuning frequency. When enabled, the range extender doubles the input frequency, and when disabled, simply passes the input frequency through. A feedback path provides a control voltage to the tank circuit to adjust the resonance frequency and thereby cause the tuning frequency to be a multiple of a reference frequency. The range extender extends the tuning frequency range over two octaves without a loss of frequency resolution. Broadly speaking, the present invention contemplates a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip. The tuner chip has a frequency doubler which provides a tuning frequency signal having a frequency twice that of an input frequency signal when the doubler is enabled, and a tuning frequency signal having a frequency equal that of an input frequency signal when the doubler is disabled. The tuner chip also has a tuning oscillator which provides the input frequency, and a downconverter coupled to receive the tuning frequency signal. The downconverter further receives a receive signal and responsively provides a product signal which is then converted to a baseband signal. The demodulator/decoder chip is configured to control the input frequency to the doubler, and further configured to convert the baseband signal to a decoded signal.


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