The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 04, 1999

Filed:

Sep. 24, 1996
Applicant:
Inventors:

Richard Gene Burch, McKinney, TX (US);

Purnendu Kanti Mozumder, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
364488 ; 364578 ; 36446804 ; 345334 ; 345340 ; 345352 ; 345420 ;
Abstract

A semiconductor structure design and process visualization tool (10). A main menu (30) allows a user to add, edit or delete process steps (16a-f) to create a process flow in process flow window (12). Main menu (30) provides a set of process models to be selected from. The set of process models are simple first-order geometric models that require only physical parameters of a resulting device layer. Specific process conditions are not required. Semiconductor process and wafer representation tool applies the physical parameters to the corresponding process model to quickly create a cross-section (20) in cross-section window (22) corresponding to a selected process step (16d) in process flow window (12).


Find Patent Forward Citations

Burch, Richard. (1999). Semiconductor structure design and process visualization through the use (U.S. Patent No. 5901062). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5901062

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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