The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 04, 1999
Filed:
Jul. 08, 1997
Michael John Gay, Vaud, CH;
Motorola, Inc., Schaumburg, IL (US);
Abstract
A current sense circuit (100) for providing an output signal (Iout) representative of a current signal (Id) flowing through a FET output device (101) comprises a first transistor (102) for providing an image current signal (I.sub.m) which is substantially proportional to the current signal flowing through the FET output device (101) until the drain-source voltage signal of the FET output device (101) is less than a predetermined voltage and a second transistor (104) coupled to a control electrode of the first transistor (102) and for coupling to the gate electrode of the FET output device (101). The first (102) and second (104) transistors are matched and have the same threshold voltages as that of the FET output device (101). The second transistor (104) provides a correction current signal (I.sub.c) when the drain-source voltage signal of the FET output device (101) is less than the predetermined voltage. Subtracting circuitry (106) coupled to the first (102) and second (104) transistors subtracts the correction current signal (I.sub.c) from the image current signal (I.sub.m) to provide a corrected image current signal which is substantially proportional to the current signal flowing through the FET output device (101). The output signal (Iout) comprises the image current signal (I.sub.m) or corrected image current signal depending on the drain-source voltage of the FET output device (101).