The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 04, 1999
Filed:
Jun. 26, 1997
Kenway W Tam, Cupertino, CA (US);
Sun Microsystems, Inc., Palo Alto, CA (US);
Abstract
A staticized flop circuit converts a dynamic signal appearing across the output of a logic circuit into a static signal, and includes a dynamic-to-static convertor which minimizes glitching in the static output. The dynamic-to-static convertor includes a pull-down device, operatively coupled between an output node and a ground, which is closed while an input node is at a precharge potential and which is open while the input node is at a ground potential, and a pull-up device, operatively coupled between a source voltage and the output node, which is closed while the input node is at the ground potential and which is open while the input node is at the precharge potential. The invertor also includes a pull-down path shutoff device, operatively coupled between the output node and the ground in series with the pull-down device, which is closed during each first phase of a clock signal and which is open during each second phase of the clock signal, and an activation device, operatively coupled between the output node and the series connection of the pull-down device and the pull-down shutoff device, which is closed during each first delayed phase of a delayed clock signal and which is open during each second delayed phase of the delayed clock signal.