The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 04, 1999

Filed:

Jun. 17, 1997
Applicant:
Inventor:

Hiroshi Kanno, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
327201 ; 327211 ; 327212 ; 327218 ; 326 28 ; 326 97 ;
Abstract

A dynamic latch circuit or a dynamic flip-flop circuit of the present invention includes a transfer gate to be controlled by a clock and provided with a complementary configuration using a P-channel and an N-channel MOS (Metal Oxide Semiconductor) transistor. The transfer gate allows the individual node included in the circuit to fully swing between a high potential power source and a low potential power source. This causes a minimum of decrease to occur in an ON current for driving the respective node and thereby realizes high-speed operation. Further, the balance of the rising time and falling time of an output signal is improved, reducing the deviation of the duty of the output signal from 50%. The circuit is therefore operable with sufficient operation margins at positive- and negative-going edges. Consequently, the entire macrocircuit using the circuit of the present invention can have its operation frequency and therefore power consumption lowered.


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