Processor having a hierarchical control register file and methods for

Abstract

A processor is provided with a number of control registers logically organized in a hierarchical manner. At the highest level is a set of control registers for controlling the overall system. At the second highest level are multiple sets of control registers for controlling concurrent execution of processes in multiple contexts. At the third highest level are multiple sets of control registers for controlling concurrent execution of multiple process threads for each of the concurrently executing contexts. Besides modifications resulting from the normal course of instruction execution, the control registers are directly accessible and modifiable using instructions of the standard instruction set. Each context/thread is assigned a variable privilege level for accessing and modifying control registers at the various levels. The instruction fetch unit is enhanced to dispatch instructions with appended context and tag identifications. The execution units are enhanced to verify a context/thread's privilege by locating the assigned privilege level using the appended context and thread identification information, before executing any instructions that access/modify a control register. Additionally, the execution units are further enhanced to be dynamically configurable in response to configuration control information stored in a thread level control register set for a thread and/or configuration information integrated with an instruction.