Processor using special instruction set to enhance exception handling

Abstract

A processor uses a special instruction set to enhance exception handling, such as interrupt handling. The processor uses a pipeline comprising five separate stages of fetch, decode, execute, memory access and register write. For each operation executed by the processor, the operation has an operation initiation instruction and an operation result fetch instruction, each of which has multiple stages. The operation result fetch instruction awaits the completion of the operation initiation instruction. While waiting, the operation result fetch instruction is suspended, preferably before any hardware resource is changed, and if necessary canceled to accommodate an exception handling signal. Since the hardware resource is changed at the 'execute' stage of the operation, the operation result fetch instruction is suspended at the 'decode' stage. Upon receiving the exception handling signal, the operation result fetch instruction may be canceled and the processor is free to process the exception handling. After completion of the exception handling, the operation result fetch instruction is re-executed from the beginning.