The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 27, 1999
Filed:
Nov. 02, 1993
Albert Van Der Werf, Eindhoven, NL;
U.S. Philips Corporation, New York, NY (US);
Abstract
Optimal design method and apparatus for synchronous digital circuits by retiming through selective flipflop positioning and electronic circuit configuration produced by executing the method. The method is for designing a synchronous digital electronic circuit that comprises cells and clocked flipflops interconnected by nets and running at a predetermined clock period, operates as follows. First, uniform-directedly as starting from any cell for any sub-path emanating therefrom its associated delay is accumulated. Next, if for such sub-path the accumulation result exceeds a predetermined integer number of clock periods. The sub-path in question is signalled for subsequent provision with such integer number of flipflops and its accumulation is terminated. Finally, all elementary cell-to-cell connections are provided with flipflops in minimal accordance with said signalling. The invention is particularly advantageous with large circuits such as used in digital video processors and with small clock periods.