The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 27, 1999
Filed:
Mar. 21, 1997
Yukio Kodama, Tokyo, JP;
Kazuo Murakami, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
When encoding data bits in a CRC code word and '0' information is received for every bit by a dividing circuit, the CRC code word is divided by a generation polynomial and remainder data resulting from the division is output from parallel data output terminals of the dividing circuit. The remainder data is added to a CRC intrinsic value in the adder to produce a sum. The sum is a CRC code in a CRC code word for transmission. When a code error is detected, data having a plurality of bits in a CRC code word and a CRC code are received by the dividing circuit, where they are divided by the generation polynomial and remainder data is output from the respective parallel data terminals. The remainder data is added to the CRC intrinsic value in the adder to produce a sum, and the sum is processed into a logical sum in a logical sum circuit. The logical sum is output as a CRC flag. The present invention provides a CRC code generation circuit for generating a CRC code in a CRC code word at high speed as well as a code error detection circuit for detecting a code error in a CRC code word at high speed.