Atm switch with integrated system bus

Abstract

A network switch includes a plurality of cell processing units coupled together via a switch bus. In a preferred embodiment, the switch bus supports the peripheral component interconnect (PCI) bus protocol. Each cell processing unit includes a segmentation and reassembly unit (SAR), a RISC processor, a port processor, and a bus control unit. The SAR generates cells from frames of data stored in memory and transfers those cells to a destination mailbox in response to commands from from the RISC processor. The SAR assembles a cell within an internal register by combining cell header information with payload data read from memory. Once a cell has been assembled, it is sent to the bus controller for transmission across the switch bus to an address given by a mailbox number. Cells are transferred across the switch bus using a PCI burst write to the mailbox. A reassembly function gathers 48-byte cells into one or more larger output buffers. Cell reassembly is triggered by another RISC processor command. During reassembly, cell header information is discarded and the data payload bytes are read to an internal buffer within the SAR. The payload data is then written to a memory location pointed to by a buffer memory pointer. The switch bus 14 is also used for the transfer of control information between configuration registers of the cell processing units 12.