The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 27, 1999
Filed:
Sep. 26, 1997
Amos Ben-Meir, Cupertino, CA (US);
Matthew P Crowley, San Jose, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
An even bus clock circuit generates logic pulses in response to substantially coincident rising edges of a processor clock and a bus clock over a given range of processor clock to bus clock ratios that includes whole integers and half integers. The even bus clock circuit includes a delay element for receiving the bus clock and generating a delayed bus clock, a first flip-flop for receiving the processor clock at a data input and receiving the delayed bus clock at a clock input, and a second flip-flop for receiving a data output of the first flip-flop at a data input, receiving the processor clock at a clock input and generating a data output that is coupled to an asynchronous reset input of the first flip-flop. The logic pulses are generated at the data output of the first flip-flop and have a pulse width of substantially the same duration as a single cycle of the processor clock.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile