Circuit and method for controlling the color balance of a flat panel

Abstract

A circuit and method for controlling the color balance of a flat panel display without losing gray scale resolution of the display screen. Within a FED screen, a matrix of rows and columns is provided and emitters are situated within each row-column intersection. Rows are activated sequentially by row drivers and corresponding individual gray scale information (voltages) is driven over the columns by column drivers. When the proper voltage is applied across the cathode and anode of the emitters, they release electrons toward a phosphor spot, e.g., red, green, blue, causing an illumination point. Within each column driver, a digital to analog converter that contains two data-in voltage-out transformation functions, a first function corresponding to a first voltage intensity and a second function corresponding to a lesser voltage intensity for a same digital color value. During the row on-time window, the present invention time multiplexes application of the voltages for the first and second functions when driving color information (e.g., voltages) over the column lines. There is a separate timing signal for each color that controls the multiplexing intervals. By adjusting the timing signal for a particular color, the intensities for all pixels of that color are adjusted up or down relative to the other colors. This provides an effective color balancing technique that does not require expansion of the color driver substrate area nor does it degrade the gray scale capability of the FED screen. Adjustment of color balancing can be done in response to tube aging and/or manufacturing variations in the phosphor.