Generation of unique address alias for memory disambiguation buffer to

Abstract

A method and device for generating address aliases corresponding to memory locations, for avoiding false load/store collisions during memory disambiguation. The alias generator takes advantage of the fact that the entire address range will most likely not be active in the registers at any one time. The subset of the address range that is active can be represented with a smaller number of bits and, hence, the computation of true dependencies is greatly reduced. The address alias generator includes an array for receiving the memory addresses, comparators having inputs connected to each array entry and having outputs connected to an alias encoder, and a control logic unit for writing the given memory address in one of the entries. The output of a given gate is turned on if a memory address is the same as the contents of one of the entry corresponding to that output, and the control means is activated if the output of all of the gates are turned off. In the preferred embodiment, the memory addresses are 32-bit values, the array has 64 entries, and the encoder generates 6-bit values for the address aliases. The processor includes a memory disambiguation buffer for identifying load/store collisions, that uses the 6-bit address aliases.