The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 27, 1999
Filed:
Dec. 19, 1996
Kuantai Yeh, Redwood City, CA (US);
Ahmad Chatila, Santa Clara, CA (US);
Shahin Sharifzadeh, Menlo Park, CA (US);
Cypress Semiconductor Corp., San Jose, CA (US);
Abstract
The present invention concerns a process that maintains a second (or 'replica') set of alignment marks during existing processing steps used in manufacturing a semiconductor device or integrated circuit, including CMP and other planarization methods. The present invention avoids alignment problems encountered in conventional CMP processes, particularly tungsten CMP. All alignment steps can be realized through one or more subsequent second (or 'replica') alignment marks, set and preserved throughout the remaining process steps, thus maintaining alignment integrity. The present method and apparatus concerns a new alignment mark that may be 'printed' in a metal layer on the wafer, for example, a local interconnect or contact layer. The new alignment mark is generally not subjected to planarization or to an 'open frame' process. The new alignment mark may also be used to re-etch other alignment marks directly onto the layer conventionally causing alignment problems, such as those created following CMP.