Bus analyzer for capturing bus signals at a predetermined rate and upon

Abstract

A GPIB system for capturing GPIB signals at a predetermined rate and upon valid transitions of the data valid signal. A first sampling circuit samples the GPIB at the predetermined rate and a second sampling circuit samples the GPIB with transitions of the data valid signal. Capture logic preferably includes data valid logic for monitoring the data valid signal to assure valid transitions. The capture logic also preferably includes select logic for selecting between the GPIB signals sampled at the predetermined rate and upon assertion of the data valid signal, where data valid signal transitions preferably have higher priority. The capture logic monitors the sampled GPIB signals and the data valid logic to enable a first-in, first-out buffer to capture sampled data upon predetermined capture conditions and upon transitions of the data valid signal. In this manner, data signal transitions which might otherwise be missed by the predetermined sampling rate are sampled and captured. Furthermore, a counter circuit is implemented to provide a time-stamp value into the buffer after each captured data value. The capture logic asserts a time-stamp signal to select the time-stamp value and also enables the buffer to capture time-stamp value into the buffer.