The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 1999
Filed:
Feb. 04, 1997
Masayuki Ikeda, Kawasaki, JP;
Shigeru Nagasawa, Kawasaki, JP;
Haruhiko Ueno, Kawasaki, JP;
Naoki Shinjo, Kawasaki, JP;
Teruo Utsumi, Kawasaki, JP;
Kazushige Kobayakawa, Kawasaki, JP;
Naoki Sueyasu, Kawasaki, JP;
Kenichi Ishizaka, Kawasaki, JP;
Masami Dewa, Kawasaki, JP;
Moriyuki Takamura, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A parallel processing apparatus and method for processing data transferred between a plurality of processors each having a storage. Each of the plurality of processors corresponds a global virtual address in a global virtual memory space where a parallel processing between the plurality of processors is performed and a local virtual address in a local virtual memory space where an individual process in one of the processors is performed to an identical real address. Data is transferred from a first one of the plurality of processors to a second one of the plurality of processors by writing the data into the storage of the second processor according to the global virtual address or the local virtual address of the second processor, the second processor is notified of the global virtual address or the local virtual address of the transferred data, the notified global virtual address or the notified local virtual address is then translated into the real address which corresponds to the notified global virtual address or the notified local virtual address, data is read from the storage of the second processor to the second processor according to the translated real address, and the read data is calculated in the second processor.