The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 1999

Filed:

Feb. 06, 1997
Applicant:
Inventors:

David A Brown, Carp, CA;

Stacy W Nichols, Kanata, CA;

Maged E Beshai, Stittaville, CA;

Assignee:

Northern Telecom Limited, Montreal, CA;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L / ;
U.S. Cl.
CPC ...
370388 ; 370412 ; 370416 ; 370395 ;
Abstract

A multi-stage ATM switch has a plurality of inlet stage fabrics, core stage fabrics and outlet stage fabrics. ATM cells routed by the switch have destination fields including (i) an identification of the outlet stage fabric and (ii) an identification of the outlet port. Cells incoming to a given inlet stage fabric are queued up in queues representing each of the outlet stage fabrics. A queue having at least the number of cells as there are core stage fabrics (or one having a lesser number of cells where cells have been waiting longer than an a pre-defined time) is identified and, in a time slot, cells are transmitted from the front of the identified queue, in parallel, one to each of the core stage fabrics (with blank make-up cells being sent, as necessary, where the identified queue had less cells than there are core stage fabrics). In the core stage fabrics, the incoming cells are again queued up in queues representing each of the outlet stage fabrics and then cells are transmitted from the heads of these queues to the outlet stage fabrics. At the outlet stage fabrics, incoming cells are queued in queues representing the outlet ports to which these cells are destined and cells are output from the heads of these queues.


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