Nonvolatile semiconductor memory device having data line dedicated to

Abstract

It is assumed that, in each memory cell array, a first bit line corresponds to a selected address. In this case, a potential on only the first bit line attains H-level. Data to be loaded is supplied to a latch circuit corresponding to the first bit line through a data line arranged independently of the bit line. All the bit lines are reset upon every completion of loading of data of 1 byte. Therefore, rapid data reading can be performed even when data is to be read from a memory cell array immediately after the data is loaded into a latch circuit, or destruction of data already loaded into the latch circuit can be prevented. Further, a circuit area can be reduced.