The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 1999
Filed:
Oct. 11, 1996
Stephen Scott Furkay, South Burlington, VT (US);
Jeffrey Bowman Johnson, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Disclosed is a method of improved grid generation for semiconductor device simulation. In particular, the invention includes a simple method for locating critical interfaces (e.g., oxide-silicon interfaces) and then utilizing the information to generate finer mesh elements near those boundaries where device behavior is most critical. The method of identifying critical interfaces includes the steps of examining the boundary data for each material region in the device, and then generating normal lines between adjacent boundaries to identify 'thin' regions, which are generally associated with the critical interfaces. Once this occurs, a recursive subdivision algorithm may be utilized to generate a grid whose element dimensions are dependent upon their proximity to identified critical regions.