Phase-locked loop circuit for generating stable clock signal for use in

Abstract

A phase-locked loop circuit generates a clock signal synchronized with a color burst signal contained in a composite color picture signal. The phase-locked loop circuit contains a phase synchronization loop having a loop gain, extracts the color burst signal from the composite color picture signal, compares the phases of the generated clock signal and the color burst signal, and controls the phase of the generated clock signal to reduce the difference between the above phases. The phase-locked loop circuit further detects the vertical blanking signal, and reduces the loop gain for the duration of the vertical blanking signal. Alternatively, a horizontal synchronizing signal is used instead of the color burst signal. Another phase-locked loop circuit generates a clock signal synchronized with a reference clock signal based on first frequency information indicating a frequency of the reference clock signal. This phase-locked loop circuit generates the clock signal so that the phase of the generated clock signal is controlled according to an output of an amplifier. Second frequency information indicating the frequency of the generated clock signal is generated, and a difference between the frequencies of the reference clock signal and the generated clock signal is obtained. The amplifier amplifies the difference with a gain which can be controlled externally. When a change in the polarity of the difference, a large amount of the absolute value of the difference, or a loss of the first information, is detected, the gain is reduced or suppressed.