Clock distribution circuit with clock branch circuits connected to

Abstract

A layout area includes a clock interconnection consisting of an upward interconnection and a downward interconnection. The upward interconnection extends from the output terminal of a clock buffer which receives an external clock signal to a turning point while passing along the vicinity of a plurality of flip-flops. The downward interconnection extends from the turning point to a free end, reversing along the upward interconnection. Clock branch circuits are provided in the vicinity of the flip-flops. The clock branch circuits have a function of letting a third clock signal make a transition when the sum of the time integral of a first clock signal on the upward interconnection and the time integral of a second clock signal on the downward interconnection has become equal to the time integral for one pulse of one of the first clock signal and the second clock signal.