Semiconductor device with a planarized interconnect with poly-plug and

Abstract

A CMOS integrated circuit structure with planarized self-aligned transistors and local planarization in the vicinity of the transistors so as to allow an interconnect, with a planar upper surface, which is free of bridging, has good continuity over the planarized topography and is compatible with self-alignment schemes, hence conserving chip real estate. The structure is compatible with planarization using BPSG, BPTEOS, SOG or CMP. After formation of self-aligned insulated transistor gates and active transistor regions, a 'landing pad' is formed on the substrate at the buried contact and polyiso contact locations so as to allow more effective etching at the exact location of the buried contact and polyiso contact. Then the integrated circuit structure is locally planarized by formation of an oxide layer and a reflowed overlying glass layer. The glass layer is etched back to planarize the surface. Then using a polyiso mask, portions of the glass layer and underlying oxide, landing pad, and nitride layers are removed in the area of a gate contact. Then using a buried contact mask, portions of the glass layer and underlying oxide, landing pad, and oxide layers are removed only in the area of the buried contact. Then a combined horizontal and vertical interconnect, with a planar upper surface, is formed to electrically connect the buried contact to the gate.