Semiconductor memory device

Abstract

A semiconductor memory device by the shared sense amplifier system, including: a sense amplifier; a plurality of bit line pairs; a plurality of word lines; a plurality of dynamic RAM cells, each of the RAM cells being connected to one bit line pair and one word line which is selected when data is read or written; switch circuit, provided for each of the plural bit line pairs, for connecting the corresponding bit line pair to said sense amplifier when the switch circuit is turned on and for disconnecting the corresponding bit line pair from said sense amplifier when the switch circuit is turned off; and bit line connection control circuit for, in order to read data from a predetermined RAM cell of the plural RAM cells in a test for detecting faults due to margin deficiency, turning on the switch circuit for the bit line pair connected to the RAM cell, and thereafter, before the word line connected to the RAM cell is selected, turning on the switch circuit for bit line pairs other than the bit line pair connected to the RAM cell, out of the plural bit line pairs.