The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 13, 1999
Filed:
Sep. 30, 1996
David B Rees, Overton, GB;
Cypress Semiconductor Corp., San Jose, CA (US);
Abstract
An augmentation circuit for use in connection with a self-bootstrap type output buffer having an n-channel pullup transistor is disclosed. The augmentation circuit includes a capacitor formed by a second n-channel transistor, connected as a capacitor, and disposed between first and second capacitor terminals. A non-overlapping signal generator is formed from a pair of NOR gates, and an inverter, to generate a pair of control signals CS1, and CS2 wherein when one of the control signals is active, the other control signal is inactive. Four n-channel transistors are provided in a switching matrix. One pair of the four n-channel transistors responds to control signal CS2 to connect the capacitor formed by the n-channel transistor across and between ground, and the output pad. In this switched configuration, a voltage level on the output pad is effectively impressed upon the capacitor, and is stored thereon. When an input signal to the buffer changes state to a logic high signal, the output of the control signals also change state, wherein the two n-channel transistors previously conducting, are now turned OFF, and the other two of the four n-channel transistors, which are controlled by CS1, are made to conduct. In this second switched configuration, the capacitor is connected across and between the positive power supply V.sub.cc, and a gate terminal of the pullup n-channel power supply. Accordingly, a voltage magnitude equal to V.sub.cc plus the pad voltage level stored on the capacitor is developed by the augmentation circuit and transferred to the gate of the pullup transistor. In another embodiment, a pair of transfer gates are used, which are controlled by a voltage level on the output node, to augment the input signal voltage level (using a stored level of approximately V.sub.cc). In a third low power embodiment, a capacitor (e.g. a p-channel device) is charged to V.sub.cc and is used to provide the required augmentation, as a function of the output node voltage.