The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 1999

Filed:

Nov. 26, 1996
Applicant:
Inventors:

Shigeru Yamaoka, Hyogo, JP;

Yutaka Ikeda, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326 83 ; 326 22 ; 326 98 ;
Abstract

In a DRAM, first and second P channel MOS transistors are connected in series between an output node of an NOR gate of an input buffer and a power supply line. The first P channel MOS transistor receives at its gate an external signal /EXT and the second P channel MOS transistor receives at its gate an inverted signal of an output enable signal OEM. In a data output period, the signal OEM attains to the 'H' level and the second P channel MOS transistor is rendered conductive, and therefore, even when power supply potential Vcc lowers in the data output period, the output node can be sufficiently charged, and an internal signal /INT can be generated stably.


Find Patent Forward Citations

Yamaoka, Shigeru. (1999). Input circuit of semiconductor memory device for generating an internal (U.S. Patent No. 5894229). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5894229

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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