The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 13, 1999
Filed:
Sep. 27, 1996
Sang-yong Lee, Kyungki-do, KR;
Soo-seong Kim, Seoul, KR;
Samsung Electronics Co., Ltd., Suwon, KR;
Abstract
An insulated gate semiconductor device includes a relatively highly doped epitaxial JFET region. The epitaxial JFET region forms a P-N junction with the base region of the device, but is spaced from the insulated gate electrode by a more lightly doped epitaxial accumulation region. The use of a spaced JFET region provides a number of important performance advantages over prior art power MOSFETs or IGBTs. By spacing the highly doped JFET region from the top face, the devices of the present invention are, among other things, capable of sustaining higher breakdown voltages without a significant increase in forward on-state resistance. For example, by using a more lightly doped accumulation region underneath the gate electrode, in place of a more highly doped JFET region, the punch-through voltage of the device is increased and electric field crowding at the base junction at the top of the face is decreased. In contrast to those JFET regions in the prior art which are formed by performing a high dose implant and/or high dose diffusion of first conductivity type dopants, the devices according to the present invention reduce the adverse influences on threshold voltage caused by high dose implants of ions adjacent the periphery of the base regions.