Structure and method for memory initialization and power on

Abstract

An SDRAM initialization and power on system includes a configuration validation circuit for registers in a Memory Controller Unit and a Power On Sequence State Machine. The validation circuit asserts a status signal Config.sub.-- OK if the configuration of the memory control unit is correct. The signal Config.sub.-- OK enables the Power On Sequence State Machine. A status signal PowerOn.sub.-- OK is asserted once the SDRAMs have been initialized. The SDRAMs are not accessible for normal operation unless Config.sub.-- OK and PowerOn.sub.-- OK are asserted. By monitoring the two signals Config.sub.-- OK and PowerOn.sub.-- OK, debugging can be much more efficient and corruption of SDRAMs with bad data can be avoided.