The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 1999

Filed:

Jun. 30, 1997
Applicant:
Inventors:

Ronald Timothy Horan, Houston, TX (US);

Gary W Thome, Tomball, TX (US);

Sompong Olarig, Cypress, TX (US);

Assignee:

Compaq Computer Corp., Houston, TX (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
39580023 ; 39580001 ; 39580028 ; 39580029 ; 39580032 ; 395821 ; 395828 ; 395859 ; 395872 ; 395882 ; 395892 ;
Abstract

A core logic chip set is provided in a computer system to provide a bridge between host and memory buses and an accelerated graphics port ('AGP') bus adapted for operation of two AGP devices, or one AGP device and one peripheral component interconnect ('PCI') device. A common AGP bus having provisions for the PCI and AGP interface signals is connected to the core logic chip set and the AGP and/or PCI device(s). The core logic chip set has an AGP/PCI arbiter having Request ('REQ') and Grant ('GNT') signal lines for each AGP and/or PCI device connected to the AGP bus. Another embodiment has a plurality of AGP buses for a plurality of AGP devices. This allows concurrent operation for AGP devices connected to different AGP buses. Two of the AGP buses may be combined to connect to one 64 bit PCI device.


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