Computer system with parallel processor for pixel arithmetic

Abstract

A pixel processor, for use in conjunction with a color video monitor or an all points addressable color print engine, includes brush logic, mask logic, clip logic, and a multi-pixel logic unit to produce a page map consisting of millions of pixels, each having a color value. To portray a 2D-rasterization of overlapping objects with portions of objects being transparent, and objects shaded with colored pattern, the processor combines source S, brush T, pattern mask, source mask, and prior destination D data. Brush logic combines an RGB color setting with a pattern to provide the brush data, tiled within a source region. Mask logic ensures transparency of portions of the pattern or source as defined by pattern mask data and source mask data, respectively. Clip logic limits pixel updates in regions of the page map not within the source region. The processor includes dynamically reconfigurable bit-slice architecture, for updating multiple pixels in parallel, for example four 8-bit pixels in one color plane per operation in a 32-bit embodiment. Registers hold intermediate results of arithmetic comparisons permitting a single raster operation such as S ((S T) & (T D)) to be performed in four clock periods. The symbol ' ' represents a function that returns the absolute value of the difference of the operands. The symbol '&' represents a function that returns the arithmetic 'minimum' of, in this case, intermediate results.