The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 1999

Filed:

Mar. 27, 1997
Applicant:
Inventors:

Mazoud Vaziri, Nepean, CA;

Maurice S O'Sullivan, Ottawa, CA;

Terry W Taraschuk, Ottawa, CA;

Alan Glen Solheim, Kanata, CA;

Kim Byron Roberts, Welwyn Garden City, GB;

Assignee:

Northern Telecom Limited, Montreal, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B / ;
U.S. Cl.
CPC ...
385-2 ; 341 57 ;
Abstract

A method for encoding a binary input sequence x(0,1) to obtain a duobinary output sequence y(+1,0,-1) is provided. The duobinary coding technique always provides an output bit y.sub.k =0 when the corresponding bit x.sub.k =0; bits y.sub.k alternatively assume a logical level '+1' and '-1' whenever an input bit x.sub.k-1 =0 changes to x.sub.k =1, and the output bit y.sub.k maintains the logical level '+1' or '-1' whenever the corresponding bit x.sub.k maintains the logical level '1'. A coding device for encoding a binary input sequence x(0,1) to a duobinary output sequence y(+1,0,-1) is also provided, comprising a D-type flip-flop for generating a binary switch signal. A first AND circuit receives the input sequence and the switch signal, and provides a first binary sequence a(0,1), while a second AND circuit receives the input sequence and the complement of the switch signal and provides a second binary sequence b(0,1). These first and second binary sequences are applied to a summer to obtain the output sequence y(+1,0,-1). A method for differentially driving a M-Z modulator using a virtual ground level is also provided, which reduces the peak-to-peak drive voltage by a factor of two.


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