The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 1999

Filed:

Dec. 23, 1997
Applicant:
Inventor:

Naoaki Kanagawa, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11L / ;
U.S. Cl.
CPC ...
365200 ; 365 63 ;
Abstract

There is provided a semiconductor memory device of a overlaid-DQ system having a column redundancy technique having high efficiency of replacing a defective address without largely increasing a chip size. Regarding DRAM of the overlaid-DQ bus type, in a metal line layer formed at an upper portion than bit lines, 256 pairs of DQ lines (DQ0 to DQ255) are formed in a form to be overlaid on the memory cell array. Each of spare circuits (a spare column, its sense amplifier (S/A), a pair of spare DQ lines (pair of SDQ lines SDQ0 to SDQ3)) is arranged per 64 pairs of DQ lines. Four sets of spare circuits may be structured as a column redundancy in connection with the 256 pairs of DQ lines, each set of spare circuits may be structured in connection with 65 pairs of DQ lines.


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